`include "defines.v"
module pipelineControl(
  input rst_n,
  // flush request
  input wbu_redict_valid_i,
  // flush signal
  output ctrl_icache_flush_o,
  output ctrl_ibf_flush_o,
  output ctrl_idu_flush_o,
  output ctrl_isu_flush_o,
  output ctrl_exu_flush_o,
  output ctrl_wbu_flush_o
);

assign ctrl_icache_flush_o = wbu_redict_valid_i;
assign ctrl_ibf_flush_o    = wbu_redict_valid_i;
assign ctrl_idu_flush_o    = wbu_redict_valid_i;
assign ctrl_isu_flush_o    = wbu_redict_valid_i;
assign ctrl_exu_flush_o    = wbu_redict_valid_i;
assign ctrl_wbu_flush_o    = wbu_redict_valid_i;

endmodule